Hardware Design of Fast Module Exponential Algorithm

Fast module exponential algorithm, fast module multiplication algorithm and fast module addition algorithm were integrated to form a hybrid fast RSA algorithm for large number operations. A hardware scheme for implementation of RSA key was proposed using the proposed algorithm. In the algorithm,m-ary method is used in the first stage to reduce multiplication times, then modified Montgomery method is used to decrease addition times, and finally fast adders and multiplication unit are made to work synchronously by adjusting their structures. A processing speed of 390 kbit/ s at 100 MHz clock was achieved for a 1 024 bit key operand.